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October 24, 2009

System Verilog Assertions – Tutorial 3

Filed under: System Verilog Assertions — Tags: , , , , , — lasic @ 1:42 pm

Lets look at the basic syntax of a system verilog assertion. 

Assertion_Label: assert property (@(<clocking>) <filter> <expression> );

The above syntax represented in a example is as follows.

req_grant_check: assert property (@(posedge clk) disable iff (rst_n) ($rose(req |=> ##[1:3] gnt));

Splitting the example into language fields:
   Assertion_Label: req_grant_check
   clocking               : posedge clk
   filter                      : disable iff (!rst_n)
   expression          : ($rose(req |=> ##[1:3] gnt)

The assertion label is used to differentiate the different assertions.
Clocking is the clock or trigger on which the assertion should be evaluated. The assertion is triggered and evaluated on this.
Filter is the condition on which the checking can be skipped. In this case we are skipping  when the reset is asserted and checking is enabled only when out of reset, Any boolean expression can be used as filter. Please note ‘iff’ is the syntax for filtering, and is not ‘if’.
Expression is the actual check that has be executed. In this case we are checking that grant should be asserted within three clocks of assertion of request.

October 20, 2009

System Verilog Assertions Tutorial – 2

Filed under: System Verilog Assertions — Tags: , , , — lasic @ 5:54 am

 

SEQUENCES

 

Properties can be created based on a single event or a sequence of events. The sequence of events are distributed over time. The sequence can be defined as follows.

 

Within 3 clocks from assertion of frame_ , the device is expected to claim the transfer by asserting devsel_. This can be represented using sequences as follows. The intent of this example is only to demonstrate a basic sequence. In future examples we will see complex usage of sequences.

 

   sequence frame_assert
       $fall(!frame_);
   endsequence
   sequence device_sel
      ##[1:3] $fall(devsel_);
   endsequence

   property transfer_init;
      @(posedge clk) frame_assert |-> device_sel;
   endproperty

   assert property (transfer_init);


 

Assertions are classified as

  • Concurrent Assertions
  • Immediate Assertions

       Concurrent assertions are clock cycle based, whereas Immediate assertions are event based. 

 

e.g. 1. PCI parity error assertion. If parity errors are seen error should be flagged.

 

//Concurrent assertion example

pci_error_chk: assert property (@(posedge clk) perr);

 

//Immediate assertion example

always_comb

begin

   pci_error2_chk: assert (perr);

end

 

As shown in the above code examples, the first property pci_error_chk is evaluated every posedge of clock. It is a declarative piece of code.

The second property pci_error2_chk is evaluated as soon as there is a change in value of perr, and is used as procedural coding in a always block.


October 19, 2009

System Verilog Assertions Tutorial – 1

Filed under: System Verilog Assertions — Tags: , , , , , , — lasic @ 1:04 pm

 

Assertion

 

An assertion is a property description. This property is being continuously evaluated in the course of simulation and if the property is not satisfied at any instant of time the assertion fails. Assertions are not a new feature and can be viewed as a monitor or checker that used to be written in Verilog using procedural code. Assertion based languages and PSL (Property Specification Language) SVA (System Verilog Assertions) provide better language constructs developed specifically for property checking. These eliminate some of the difficulties encountered when using a procedural code like verilog.

SVA is declartive code and meant specifically for property checking. Lets look at an example temporal check.
e.g. 1. Arbiter
The request to the arbiter is asserted on the posedge of the clock. The grant should be asserted within a maximum of 60 clocks. If the particular device doesnt get a grant within 50 clocks then the arbiter logic fails.

req_grant_checker_devA:
assert propery (@(posedge clk) $rose(req) | -> ##[1:50] $rose(grant));

The same checker written in procedural verilog could have ended up very verbose.

Having learnt what is the advantage of assertion based verification, lets get into details of the language in future tutorials. Happy Blogging.


System Verilog, An intro to the tutorials in store

Filed under: System Verilog, Verification Languages — Tags: , , , , , , , , , , — lasic @ 11:57 am

System Verilog is the world’s first HDVL (Hardware Design Verification Language).
The other languages like ‘e’ and ‘Vera’ have been HVLs (Hardware Verification Languages.

System Verilog has features for

  • RTL Design
    
  • Assertions
    
  • Verification

System Verilog has evolved borrowing features and aspects from

  • Verilog
  • Superlog
  • VHDL
  • PSL (Property Specification Language)
    
  • C
    
  • Vera

 
In the series of tutorials that we plan to publish, we will see the features of System Verilog including but not limited to
   

  • Data Types
    
  • Enum, struct, union, typedef
    
  • Packed and unpacked arrays/structs
    
  • Packages
    
  • Multidimensional Arrays
    
  • Strings
    
  • Dynamic Arrays
    
  • Associative Arrays
  • Classes with single inheritance
    
  • Constraints
    

Control and Procedural Statements
       

  1. if, case
        
  2. for, foreach, while, do while, 
  3. repeat, forever
        
  4. break, continue, return
    
  • Functions and Procedures
    
  • Fork, suspend, kill, wait, disable
    
  • DPI (Direct Programming Interface)
    
  • always_ff
    always_latch
    always_comb
    
  • Interfaces, Virtual Interaces, Advanced interfaces
    
  • Semaphore, Mailbox, Enhanced Events
  • Queues, Linked List
    
  • Constraint Randomization
    
  • Functional Coverage (covergroups, coverpoints)

We will go into detailed examples discussing all these features in the coming days. Happy Blogging.

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