Assertion
An assertion is a property description. This property is being continuously evaluated in the course of simulation and if the property is not satisfied at any instant of time the assertion fails. Assertions are not a new feature and can be viewed as a monitor or checker that used to be written in Verilog using procedural code. Assertion based languages and PSL (Property Specification Language) SVA (System Verilog Assertions) provide better language constructs developed specifically for property checking. These eliminate some of the difficulties encountered when using a procedural code like verilog.
SVA is declartive code and meant specifically for property checking. Lets look at an example temporal check.
e.g. 1. Arbiter
The request to the arbiter is asserted on the posedge of the clock. The grant should be asserted within a maximum of 60 clocks. If the particular device doesnt get a grant within 50 clocks then the arbiter logic fails.
req_grant_checker_devA:
assert propery (@(posedge clk) $rose(req) | -> ##[1:50] $rose(grant));
The same checker written in procedural verilog could have ended up very verbose.
Having learnt what is the advantage of assertion based verification, lets get into details of the language in future tutorials. Happy Blogging.
