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October 20, 2009

System Verilog Assertions Tutorial – 2

Filed under: System Verilog Assertions — Tags: , , , — lasic @ 5:54 am

 

SEQUENCES

 

Properties can be created based on a single event or a sequence of events. The sequence of events are distributed over time. The sequence can be defined as follows.

 

Within 3 clocks from assertion of frame_ , the device is expected to claim the transfer by asserting devsel_. This can be represented using sequences as follows. The intent of this example is only to demonstrate a basic sequence. In future examples we will see complex usage of sequences.

 

   sequence frame_assert
       $fall(!frame_);
   endsequence
   sequence device_sel
      ##[1:3] $fall(devsel_);
   endsequence

   property transfer_init;
      @(posedge clk) frame_assert |-> device_sel;
   endproperty

   assert property (transfer_init);


 

Assertions are classified as

  • Concurrent Assertions
  • Immediate Assertions

       Concurrent assertions are clock cycle based, whereas Immediate assertions are event based. 

 

e.g. 1. PCI parity error assertion. If parity errors are seen error should be flagged.

 

//Concurrent assertion example

pci_error_chk: assert property (@(posedge clk) perr);

 

//Immediate assertion example

always_comb

begin

   pci_error2_chk: assert (perr);

end

 

As shown in the above code examples, the first property pci_error_chk is evaluated every posedge of clock. It is a declarative piece of code.

The second property pci_error2_chk is evaluated as soon as there is a change in value of perr, and is used as procedural coding in a always block.


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