In this edit, lets see the advancement is System Verilog over traditional Verilog as for as timescale is concerned.
In verilog lets see how a clock is implemented.
reg clock;
initial clock <= 1′b0;
forever #10 clock <= ~clock;
In the above example what is the frequency of the clock generated????
The answer is not readily available since it depends on more factors. It depends on the `timescale directive.
`timescale 1ns/10ps
The problem with depending on a compiler directive timescale is that, compiler directives are influenced by the compile order of the source code.
This issue has been pretty well fixed in System Verilog. In SV we can specify timescale and precision for each module and much more importantly its not a compiler directive.
These are implemented as declarative statements.
timeunits 1ns;
timeprecision 10ps;
The units specified for timeunits and timeprecision can be
s – seconds
ms – milliseconds
ns – nanoseconds
ps – picoseconds
fs – femtoseconds
There is one more option available is SV, you can even specify the timeunits in the clock declartion as below:
reg clock;
initial clock <= 1′b0;
forever #10ns clock <= ~clock;
Here we see that we can directly say #1ons as the clock period.
