System Verilog is the world’s first HDVL (Hardware Design Verification Language).
The other languages like ‘e’ and ‘Vera’ have been HVLs (Hardware Verification Languages.
System Verilog has features for
- RTL Design
- Assertions
- Verification
System Verilog has evolved borrowing features and aspects from
- Verilog
- Superlog
- VHDL
- PSL (Property Specification Language)
- C
- Vera
In the series of tutorials that we plan to publish, we will see the features of System Verilog including but not limited to
- Data Types
- Enum, struct, union, typedef
- Packed and unpacked arrays/structs
- Packages
- Multidimensional Arrays
- Strings
- Dynamic Arrays
- Associative Arrays
- Classes with single inheritance
- Constraints
Control and Procedural Statements
- if, case
- for, foreach, while, do while,
- repeat, forever
- break, continue, return
- Functions and Procedures
- Fork, suspend, kill, wait, disable
- DPI (Direct Programming Interface)
- always_ff always_latch always_comb
- Interfaces, Virtual Interaces, Advanced interfaces
- Semaphore, Mailbox, Enhanced Events
- Queues, Linked List
- Constraint Randomization
- Functional Coverage (covergroups, coverpoints)
We will go into detailed examples discussing all these features in the coming days. Happy Blogging.
