liveasic.com Blog » System Verilog http://liveasic.com/blog Just another WordPress weblog Wed, 11 Nov 2009 14:38:58 +0000 http://wordpress.org/?v=2.8.4 en hourly 1 System Verilog Assertions – Tutorial 3 http://liveasic.com/blog/2009/10/24/system-verilog-assertions-tutorial-3/ http://liveasic.com/blog/2009/10/24/system-verilog-assertions-tutorial-3/#comments Sat, 24 Oct 2009 13:42:26 +0000 lasic http://liveasic.com/blog/?p=50 Lets look at the basic syntax of a system verilog assertion. 

Assertion_Label: assert property (@(<clocking>) <filter> <expression> );

The above syntax represented in a example is as follows.

req_grant_check: assert property (@(posedge clk) disable iff (rst_n) ($rose(req |=> ##[1:3] gnt));

Splitting the example into language fields:
   Assertion_Label: req_grant_check
   clocking               : posedge clk
   filter                      : disable iff (!rst_n)
   expression          : ($rose(req |=> ##[1:3] gnt)

The assertion label is used to differentiate the different assertions.
Clocking is the clock or trigger on which the assertion should be evaluated. The assertion is triggered and evaluated on this.
Filter is the condition on which the checking can be skipped. In this case we are skipping  when the reset is asserted and checking is enabled only when out of reset, Any boolean expression can be used as filter. Please note ‘iff’ is the syntax for filtering, and is not ‘if’.
Expression is the actual check that has be executed. In this case we are checking that grant should be asserted within three clocks of assertion of request.

]]> http://liveasic.com/blog/2009/10/24/system-verilog-assertions-tutorial-3/feed/ 0 System Verilog, An intro to the tutorials in store http://liveasic.com/blog/2009/10/19/system-verilog-an-intro-to-the-tutorials-in-store/ http://liveasic.com/blog/2009/10/19/system-verilog-an-intro-to-the-tutorials-in-store/#comments Mon, 19 Oct 2009 11:57:23 +0000 lasic http://liveasic.com/blog/?p=15 System Verilog is the world’s first HDVL (Hardware Design Verification Language).
The other languages like ‘e’ and ‘Vera’ have been HVLs (Hardware Verification Languages.

System Verilog has features for

  • RTL Design
    
  • Assertions
    
  • Verification

System Verilog has evolved borrowing features and aspects from

  • Verilog
  • Superlog
  • VHDL
  • PSL (Property Specification Language)
    
  • C
    
  • Vera

 
In the series of tutorials that we plan to publish, we will see the features of System Verilog including but not limited to
   

  • Data Types
    
  • Enum, struct, union, typedef
    
  • Packed and unpacked arrays/structs
    
  • Packages
    
  • Multidimensional Arrays
    
  • Strings
    
  • Dynamic Arrays
    
  • Associative Arrays
  • Classes with single inheritance
    
  • Constraints
    

Control and Procedural Statements
       

  1. if, case
        
  2. for, foreach, while, do while, 
  3. repeat, forever
        
  4. break, continue, return
    
  • Functions and Procedures
    
  • Fork, suspend, kill, wait, disable
    
  • DPI (Direct Programming Interface)
    
  • always_ff
    always_latch
    always_comb
    
  • Interfaces, Virtual Interaces, Advanced interfaces
    
  • Semaphore, Mailbox, Enhanced Events
  • Queues, Linked List
    
  • Constraint Randomization
    
  • Functional Coverage (covergroups, coverpoints)

We will go into detailed examples discussing all these features in the coming days. Happy Blogging.

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