liveasic.com Blog » Verification http://liveasic.com/blog Just another WordPress weblog Wed, 11 Nov 2009 14:38:58 +0000 http://wordpress.org/?v=2.8.4 en hourly 1 System Verilog Assertions Tutorial – 1 http://liveasic.com/blog/2009/10/19/system-verilog-assertions-tutorial-1/ http://liveasic.com/blog/2009/10/19/system-verilog-assertions-tutorial-1/#comments Mon, 19 Oct 2009 13:04:54 +0000 lasic http://liveasic.com/blog/?p=24  

Assertion

 

An assertion is a property description. This property is being continuously evaluated in the course of simulation and if the property is not satisfied at any instant of time the assertion fails. Assertions are not a new feature and can be viewed as a monitor or checker that used to be written in Verilog using procedural code. Assertion based languages and PSL (Property Specification Language) SVA (System Verilog Assertions) provide better language constructs developed specifically for property checking. These eliminate some of the difficulties encountered when using a procedural code like verilog.

SVA is declartive code and meant specifically for property checking. Lets look at an example temporal check.
e.g. 1. Arbiter
The request to the arbiter is asserted on the posedge of the clock. The grant should be asserted within a maximum of 60 clocks. If the particular device doesnt get a grant within 50 clocks then the arbiter logic fails.

req_grant_checker_devA:
assert propery (@(posedge clk) $rose(req) | -> ##[1:50] $rose(grant));

The same checker written in procedural verilog could have ended up very verbose.

Having learnt what is the advantage of assertion based verification, lets get into details of the language in future tutorials. Happy Blogging.


]]> http://liveasic.com/blog/2009/10/19/system-verilog-assertions-tutorial-1/feed/ 0 System Verilog, An intro to the tutorials in store http://liveasic.com/blog/2009/10/19/system-verilog-an-intro-to-the-tutorials-in-store/ http://liveasic.com/blog/2009/10/19/system-verilog-an-intro-to-the-tutorials-in-store/#comments Mon, 19 Oct 2009 11:57:23 +0000 lasic http://liveasic.com/blog/?p=15 System Verilog is the world’s first HDVL (Hardware Design Verification Language).
The other languages like ‘e’ and ‘Vera’ have been HVLs (Hardware Verification Languages.

System Verilog has features for

  • RTL Design
    
  • Assertions
    
  • Verification

System Verilog has evolved borrowing features and aspects from

  • Verilog
  • Superlog
  • VHDL
  • PSL (Property Specification Language)
    
  • C
    
  • Vera

 
In the series of tutorials that we plan to publish, we will see the features of System Verilog including but not limited to
   

  • Data Types
    
  • Enum, struct, union, typedef
    
  • Packed and unpacked arrays/structs
    
  • Packages
    
  • Multidimensional Arrays
    
  • Strings
    
  • Dynamic Arrays
    
  • Associative Arrays
  • Classes with single inheritance
    
  • Constraints
    

Control and Procedural Statements
       

  1. if, case
        
  2. for, foreach, while, do while, 
  3. repeat, forever
        
  4. break, continue, return
    
  • Functions and Procedures
    
  • Fork, suspend, kill, wait, disable
    
  • DPI (Direct Programming Interface)
    
  • always_ff
    always_latch
    always_comb
    
  • Interfaces, Virtual Interaces, Advanced interfaces
    
  • Semaphore, Mailbox, Enhanced Events
  • Queues, Linked List
    
  • Constraint Randomization
    
  • Functional Coverage (covergroups, coverpoints)

We will go into detailed examples discussing all these features in the coming days. Happy Blogging.

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