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What We Do
Contribute towards the ASIC-FPGA design and verification community as a resource and reference point.
We look forward to contribute as a learning resource and discussion forum on latest, standard and legacy design verification trends:
- System Verilog
- Open Vera
- Verilog, VHDL
- SOC bus interfaces
- Design and Verification methodologies
- Design and Verification IPs
- Protocols and Standards
Coming Soon!!!
USB 3.0...
PCIExpress 3.0...
AXI...
AHB...
PCI...
Wishbone...
OCP...
Aurora...
SMBUS...
HMDI...
Ethernet...
LTE...
WiMax...
